`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/10/23 15:58:43
// Design Name: 
// Module Name: top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module top(
  clk,
  rst,
  en,
  sig_mult_I,
  baseband_Ilow,
  baseband_Qlow,
  baseband_I,
  baseband_Q
    );
input clk;
input rst;
input en;

output [31:0] sig_mult_I;
wire [31:0] sig_mult_Q;
wire [32:0] mod_dout;
output [11:0] baseband_Ilow;
output [11:0] baseband_Qlow;
output [23:0] baseband_I;
output [23:0] baseband_Q;

mod_16QAM mod_16QAM(
    .clk(clk),
    .rst(rst),
    .sig_mult_I(sig_mult_I),
    .sig_mult_Q(sig_mult_Q),
    .mod_dout(mod_dout),
    .baseband_Ilow(baseband_Ilow),
    .baseband_Qlow(baseband_Qlow),
    .baseband_I(baseband_I),
    .baseband_Q(baseband_Q)
    );
 
 
endmodule
